1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device and a system and method of testing the semiconductor memory device.
2. Discussion of Related Art
To test a semiconductor memory device, a tester may provide address signals to the semiconductor memory device through address pins, command signals through command pins, and data through DQ pins.
In general, the tester is comprised of a limited number of channels. Therefore, as the number of pins of a semiconductor memory device used for a test is increased, the number of semiconductor memory devices that can be tested at the same time may be decreased.
There exists a need for a method to increase the number of semiconductor memory devices that may be tested simultaneously.